DocumentCode :
3502384
Title :
Power gating with multiple sleep modes
Author :
Agarwal, Kanak ; Deogun, Harmander ; Sylvester, Dennis ; Nowka, Kevin
Author_Institution :
IBM Res., Austin, TX
fYear :
2006
fDate :
27-29 March 2006
Lastpage :
637
Abstract :
This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. Our simulations and data traces show that multiple sleep mode capability provides an extra 17% reduction in overall leakage as compared to single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit
Keywords :
integrated circuit design; leakage currents; nanoelectronics; high wake-up latency; leakage savings; multiple sleep modes; power gating; wake-up overhead; wake-up power penalty; Circuits; Delay; Logic; MOS devices; Power dissipation; Rails; Runtime; Steady-state; Threshold voltage; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
Type :
conf
DOI :
10.1109/ISQED.2006.102
Filename :
1613208
Link To Document :
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