Title :
Transistor-level optimization of supergates
Author :
Kagaris, Dimitris ; Haniotakis, Themistoklis
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL
Abstract :
The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach
Keywords :
VLSI; circuit optimisation; integrated circuit design; logic gates; transistor circuits; complex gates; digital VLSI design; supergates; transistor level optimization; Circuits; Cost function; Delay; Design optimization; Logic design; Logic functions; Logic gates; Network synthesis; Process design; Very large scale integration;
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.139
