DocumentCode :
3502580
Title :
The influences of grain size distributions on thermal-stresses in Cu-TSV
Author :
Yucheng Ma ; Zhiheng Huang ; Zhiyong Wu ; Dong Wu ; Yong Zhang
Author_Institution :
Sch. of Phys. & Eng., Sun Yat-sen Univ., Guangzhou, China
fYear :
2012
fDate :
13-16 Aug. 2012
Firstpage :
330
Lastpage :
335
Abstract :
The dimensions of copper through-silicon vias (Cu-TSVs) have been shrunk to a microscopic scale, where the sizes of the copper grains are comparable to the vias, and thus the microstructure of the copper in the vias should be taken into consideration for reliability predictions. This paper focuses on the influences of the grain size distributions on the thermal-mechanical behaviors of the TSVs. Copper grains in TSVs are generated by both the Voronoi algorithm and a phase field method. The equations relating the yield stress and the Young´s modulus with respect to grain size are derived from experimental data. Two different boundary conditions are applied to the TSV models in the thermal-mechanical simulations and the thermal stresses of the microstructural models are calculated using the finite element method (FEM). The results from the microstructural models are then compared with the results from the reference model which ignores the grain structures. The results show that the copper grains can influence the thermal stresses in the via with negligible effects on other regions of the TSV. Smaller grains result in higher stresses, and the increase in stress can be as high as 30 MPa. The influence of the grain size distribution on thermal stress depends on the location of the grains as well as the applied boundary conditions. The grains with similar sizes in different grain structures can exhibit a difference in thermal stress around 10 MPa, whereas a difference in the boundary condition can lead to a completely different stress distribution.
Keywords :
computational geometry; copper; finite element analysis; grain size; integrated circuit modelling; integrated circuit reliability; thermal stresses; three-dimensional integrated circuits; yield stress; FEM; TSV model; Voronoi algorithm; Young modulus; boundary condition; copper TSV; copper grains; copper microstructure; copper through-silicon vias dimension; finite element method; grain size distributions; grain structures; microstructural models; phase field method; reference model; reliability predictions; stress distribution; thermal stresses; thermal-mechanical behaviors; thermal-mechanical simulations; yield stress; Annealing; Copper; Microstructure; Stress; Thermal expansion; Thermal stresses; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4673-1682-8
Electronic_ISBN :
978-1-4673-1680-4
Type :
conf
DOI :
10.1109/ICEPT-HDP.2012.6474628
Filename :
6474628
Link To Document :
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