Title :
The challenges and impact of parasitic extraction at 65 nm
Author_Institution :
Mentor Graphics, Wilsonville, CA
Abstract :
Although industry-wide adoption of 65nm technology is in its infancy, major foundries have started developing design kits for the 65nm base. For designers, this means managing new and complex process variability and interconnect issues, relevant to specific design flows, using advanced parasitic extraction methodologies
Keywords :
foundries; integrated circuit manufacture; nanoelectronics; 65 nm; industry wide adoption; parasitic extraction; process variability; Delay effects; Digital circuits; Foundries; Graphics; Integrated circuit interconnections; Manufacturing; Switching circuits; Threshold voltage; Transistors; Wire;
Conference_Titel :
Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2523-7
DOI :
10.1109/ISQED.2006.133
