Low Complexity Hardware Implementation of V-BLAST Receiver

This paper presents a simplified V-BLAST (vertical bell lab layered spaced-time) detection algorithm from the hardware implement perspective. Simulation shows that the BER (Bit Error Rate) performance is close to Golden detection algorithm, but the complexity is greatly less. Then the paper provides an efficient hardware structure to implement this algorithm in FPGA (field programmable gate array), which can be used in the B3G TDD-MIMO-OFDM (Beyond 3G Time-Duplex-Division Multi-Input Multi-Output Orthogonal frequency division multiplexing) system. By applying bit-width reduction technique, the fabrication area it takes can be significantly reduced. In uplink, we adopted 4 transmit and 8 receive antennas. The implementation with Virtex square Pro Series FPGA was verified to be worked well in B3G system.