Title :
Performance evaluation of reusable multipliers for rapid prototyping
Author :
Rodellar, Victoria ; Sacristan, Miguel A. ; Gomez, Pedro ; Diaz, Antonio ; Peinado, Virginia
Author_Institution :
Fac. de Inf., Univ. Politecnica de Madrid, Spain
Abstract :
A reusable multiplier operating in fixed-point and two´s complement arithmetic is introduced. The data format and operand sizes can be adapted to the precision requirements for any particular DSP application. The algorithmic basis of the device resides in the utilization of signed digit arithmetic representation that allows an important degree of independence between the critical path delay and operands size. The model is written in VHDL. The performance results in terms of area requirement and critical path delay for Vixtex FPGA and 0.6 μm AMS technologies are evaluated
Keywords :
delays; digital arithmetic; field programmable gate arrays; fixed point arithmetic; hardware description languages; high level synthesis; integrated circuit design; multiplying circuits; performance evaluation; 0.6 micron; DSP application; VHDL library multiplier; Vixtex FPGA; critical path delay; data format; fixed-point arithmetic; operand sizes; partial products accumulation; partial products generation; performance evaluation; rapid prototyping; reusable multiplier; signed digit arithmetic representation; submicron AMS technologies; two´s complement arithmetic; Circuit synthesis; Control systems; Delay; Digital signal processing; Field programmable gate arrays; Fixed-point arithmetic; Hardware design languages; High level synthesis; Prototypes; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951660
