Ultra thin die assembly process for high power RF applications

The main driver for die thickness reduction in high power RF base station applications is the increase in product performance, particularly RF power efficiency. Reducing the metal oxide semiconductor capacitor (MOScap) thickness minimizes loss in the RF power transistor product. However, the assembly process of such thin dies presents certain difficulties, especially in die attach processing. This study outlines the technical challenge in achieving corner-chipout free die attach process with 50μm thin MOScap die in gold-silicon (AuSi) eutectic die attach on copper-pressed copper molybdenum-copper (CPC) heatsink. Process and material characterization were conducted to understand the combined behavior and influence of different factors in the die attach process. Some of the techniques like three-point bend test for die strength characterization, thermo-mechanical modeling for die stress analysis, surface profiling for flatness and roughness measurements, process mapping to capture the occurrence of corner chipout and design of experiments for die attach process feasibility were implemented in this study. Reliability testing was conducted to evaluate the robustness of the product with 50μm thin MOScap dies. It was found that the die aspect ratio and die attach scrubbing processes play dominant role in achieving a corner-chipout free die attach process. Decreasing die aspect ratio as well as reducing die attach scrub parameters to a certain minimum requirement will result in lower corner chipout risk. Thermal cycling (TMCL) results demonstrated that 50μm thin MOScap dies are robust enough to withstand product life time specification. In summary, this feasibility study showed that by optimizing the die attach parameters a corner-chipout free process can be achieved. The knowledge gained and the results achieved in this study served as a catalyst in further development of the thin MOScap die technology.