Components of a 12-bit 50 Ms/s non-radix 2 pipeline analog-to-digital converter

Author

Liu, Hui ; Du, Xiaohong ; Hassoun, Maman

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

400

Abstract

The design and implementation of the components of a non-radix 2 12-bit pipeline analog-to-digital converter (ADC) is presented in this paper. The ADC is composed of 13 pipeline stages each with a gain of 1.9 rather than the traditional 2. Each stage of the pipeline is composed of a fully differential sample and hold amplifier (SHA), a 1-bit sub-ADC and a 1-bit sub-DAC. The sub-DAC functionality is rolled in as part of the SHA switched-capacitor circuit, which is referred to as the multiplying DAC (MDAC). The ADC has been implemented in a 0.35 μm single-poly CMOS digital process

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; sample and hold circuits; switched capacitor networks; 0.35 micron; 12 bit; S/H amplifier SC circuit; fully differential amplifier; multiplying DAC; nonradix 2 pipeline ADC; pipeline analog-to-digital converter; sample/hold amplifier; single-poly CMOS digital process; sub-DAC; switched-capacitor circuit; Analog-digital conversion; Boosting; CMOS process; Design engineering; Differential amplifiers; Frequency; Instruments; Pipelines; Safety; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951668

Filename

951668