• DocumentCode
    3503266
  • Title

    Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism

  • Author

    Lin, Chia-Yu ; Ku, Mong-Kai ; Chien, Yi-Hsing

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    2008
  • fDate
    11-14 May 2008
  • Firstpage
    1423
  • Lastpage
    1427
  • Abstract
    In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with quasi-cyclic (QC) LDPC codes at long block lengths. A modified progressive edge-growth algorithm is used to construct the hierarchical quasi-cyclic (H-QC) LDPC codes. By adding implementation-friendly two-level hierarchy with limited types of second-level submatrices in the parity check matrix, coding performance is improved substantially over QC codes. We also show that QC-based decoder architecture can be easily applied to H-QC decoders to achieve better coding gain and higher throughput performance. Moreover, the degree of decoding parallelism and code length can be adjusted by changing the H-QC code construction parameters.
  • Keywords
    cyclic codes; decoding; parity check codes; H-QC decoder; edge-growth algorithm; long length quasi cyclic LDPC code construction; parity check matrix; Codecs; Computer errors; Decoding; Floors; Hardware; Parallel processing; Parity check codes; Performance gain; Sparse matrices; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE
  • Conference_Location
    Singapore
  • ISSN
    1550-2252
  • Print_ISBN
    978-1-4244-1644-8
  • Electronic_ISBN
    1550-2252
  • Type

    conf

  • DOI
    10.1109/VETECS.2008.299
  • Filename
    4525855