DocumentCode :
3503324
Title :
DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors
Author :
Albrecht, C. ; Foag, J. ; Koch, R. ; Maehle, E.
Author_Institution :
University of Lubeck, Lubeck, Germany
fYear :
2006
fDate :
15-17 Feb. 2006
Firstpage :
101
Lastpage :
108
Abstract :
Network processors are special purpose processors, tailored to the needs of packet processing in internet routers. Network processors are, in general, freely programmable devices. However, their performance in payload processing relies on specific tasks to be accelerated by fixed purpose coprocessors which are integrated into the device. As a solution to overcome the restrictions of flexibility, a dynamically adaptable coprocessor based on dynamically and partially reconfigurable logic (DynaCORE) is proposed.
Keywords :
Bandwidth; Computer architecture; Computer networks; Coprocessors; Costs; Field programmable gate arrays; Hardware; Payloads; Reconfigurable logic; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel, Distributed, and Network-Based Processing, 2006. PDP 2006. 14th Euromicro International Conference on
Conference_Location :
Montbeliard-Sochaux, France
ISSN :
1066-6192
Print_ISBN :
0-7695-2513-X
Type :
conf
DOI :
10.1109/PDP.2006.30
Filename :
1613259
Link To Document :
بازگشت