Title :
Layout generation for low-power NMOS 4-phase dynamic logic array
Author :
Furuie, Makoto ; Song, Bao-Yu ; Yoshida, Yukihiro ; Onoye, Takao ; Shirakawa, Isao
Author_Institution :
Dept. Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M×N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the NMOS 4-phase dynamic logic
Keywords :
MOS logic circuits; circuit layout CAD; integrated circuit layout; logic CAD; logic arrays; low-power electronics; NMOS; array cell architecture; density; four-phase dynamic logic array; layout generation; logic macro; low-power design; low-power dissipation; low-power electronics; structure regularity; total layout area; CMOS logic circuits; Clocks; Delay; Frequency; Logic arrays; Logic functions; Logic gates; MOS devices; MOSFETs; Variable structure systems;
Conference_Titel :
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location :
Cheju Island
Print_ISBN :
0-7803-5739-6
DOI :
10.1109/TENCON.1999.818557
