Efficient analog architectures for DCT processing

This paper presents for the first time full analog design of three different algorithms for 8 × 8 two Dimensional (2-D) Discrete Cosine Transform (DCT), using current-mode analog modules. The operation of each processor is explained with block diagrams and circuit diagrams. All these three structures need no memory. Next, three algorithms which are implemented in analog domain, are compared with respect to the number of transistors and power dissipation. Finally, the architecture with matrix simplification is chosen for simulation as it needs only 2752 transistors and dissipates less power, compared to other two architectures. The entire analog 2-D DCT processor has been implemented and laid out in UMC 0.18- µm technology. The post layout simulation results show that average PSNR is 25.6 dB, maximum power dissipation is 5.67 mW and transform speed is less than 70 nS.