A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design

Author

Yan, Jie ; Geiger, Randall L.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

502

Abstract

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the output conductance of a transistor, as opposed to a transconductance or some other parameters, to enhance tracking over process and environment variations. A single stage CMOS op amp was designed using this technique that achieved a simulated DC gain of 83 dB

Keywords

CMOS analogue integrated circuits; high-speed integrated circuits; low-power electronics; negative resistance circuits; operational amplifiers; 83 dB; CMOS op amp design; DC gain; circuit technique; low-voltage high-speed operation; negative conductance; output conductance; voltage gain; Equivalent circuits; Feedback; Frequency; Impedance; Low voltage; Operational amplifiers; Performance gain; Power dissipation; Stacking; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951693

Filename

951693