Effects of via pitch on silicon stress in TSV interposer

Through silicon vias (TSVs) have been extensively studied because it is a key enabling technology for achieving three dimensional (3D) chip stacking and silicon interposer interconnection. The large mismatch between the coefficients of thermal expansion (CTE) of copper and silicon induces stress which is critical for the TSV reliability performance. This paper proposes analytical solutions of stress in a single TSV subjected to thermal loading. Then the thermal stress interaction between the vias induced on silicon has been investigated using finite element modeling. It indicates that the interaction of thermal stress between vias becomes insignificant as long as the ratio of pitch to diameter of TSVs reaches three.