Design and implementation of a radiation tolerant on-board computer for science technology satellite-3

This paper describes the design and implementation of a radiation tolerant on-board computer (OBC) for the science and technology satellite-3 (STSAT-3). SRAM-based FPGAs are replacing traditional integrated circuits for space applications. However, it is difficult to employ the approach in space applications without radiation tolerant schemes to deal with the radiation effects such as single event upset (SEU). To mitigate the SEU effect, we apply a triple modular redundancy (TMR) scheme to the STSAT-3 OBC based on FPGA. Although there is an overhead in area, power and minimum clock period, we notice through a radiation test in an irradiation facility that our TMR based OBC is immune to the radiation environments up to a proton energy of 20.3MeV. The radiation environment of the test is expected to be more severe than the environment in which STSAT-3 is to be located.