Title :
A 300 MHz burst-pipelined CMOS SRAM macro with folded bit-line scheme
Author :
Kim, Sejun ; Chang, Ilkwon ; Song, Byunggeun ; Park, Jaegeun ; Kwack, Kaedal
Author_Institution :
Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
This paper describes a new architecture and schemes for high speed SRAM. It is summarized as follows: (1) a folded bit-line architecture (FBLA) to reduce the delay time of bit-line by decreasing the parasitic capacitance, to reduce the area; (2) a double word-line activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and (3) a high speed sensing scheme to decrease the delay time of sense amplifier. To verify these, a 8 Kb SRAM was designed using 0.6 μm technology; it realized a 600 Mbyte/s (300 M×8×2) data-rate and the die size is 2.8 mm×0. 85 mm
Keywords :
CMOS memory circuits; SRAM chips; capacitance; cellular arrays; delays; high-speed integrated circuits; parallel memories; pipeline processing; 0.6 micron; 300 MHz; 600 Mbyte/s; 8 Kbit; burst-pipelined CMOS SRAM macro; delay time; die size; double word-line activation; folded bit-line scheme; high speed sensing scheme; parasitic capacitance; row path delay; sense amplifier; Capacitance; Circuits; Clocks; Decoding; Delay effects; Large-scale systems; Microprocessors; Pipelines; Random access memory; Voltage;
Conference_Titel :
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location :
Cheju Island
Print_ISBN :
0-7803-5739-6
DOI :
10.1109/TENCON.1999.818600
