Thermal resistance analysis by numerical method for power device packaging

Thermal resistance is a key thermal parameter to determine the junction temperature of the electronic device and give reference to further thermal design in complex applications both for manufacturer and user. In this paper, junction to case resistance(R_θJC) measurement of power device in TO3P package is provided with ANSYS finite element analysis model under two different boundary conditions. The method and model in simulation employed in this analysis is verified by correlating with the value in the datasheet of real package device. Consequently, the validated method was used to investigate the influence of power load, case temperature, material parameter and die size on R_θJC. It is found that R_θJC has positive correlation with the heating power and case temperature because of the negative relation between temperature and the thermal conductivity of silicon. Besides, R_θJC of TO3P package is more sensitive to the change of thermal conductivity of die attach than that of epoxy mould compound. It also reveals that TO3P package is more suitable for packaging large chips in terms of reducing R_θJC.