• DocumentCode
    3504816
  • Title

    Application of finite element simulation on package failure analysis and problem solving

  • Author

    Weidong Huang

  • Author_Institution
    Freescale Semicond. (China) Ltd., Tianjin, China
  • fYear
    2012
  • fDate
    13-16 Aug. 2012
  • Firstpage
    799
  • Lastpage
    802
  • Abstract
    Finite Element Simulation is a powerful method to figure out the failure root causes in IC packaging or verify the solution proposals for problem solving. This paper presents three typical cases occurring in package development or mass production respectively regarding to die crack, wire heel crack and warpage-induced process issue. Die crack is a typical failure mode and is found frequently when qualifying a new package product. In some cases, a common phenomenon is observed in different packages with die crack issue: over-high epoxy fillets attached on the cracking die sides for all failed units. In the first case, based on the assumption that over-high fillet has more potentiality to spread the delamination to the die top edge, the simulation result reveals that the structure of over-high fillet plus the delamination at the die top edge should be a severe risk to lead to die crack. Wire heel crack is also a typical failure mode which could be observed after the temperature cycle tests. In the second case, the modeling result reveals that CTE mismatch between the gold wire and the molding compound at low temperature (-65°C) induced the thermal stress which tension the stitch bond. Delamination along the lead frame surface around the stitch bond causes the large plastic deformation at the bottom of the stitch bond and leads to wire heel crack. Thus delamination is a crucial factor that causes the heel crack. Warpage-induced process issue on production line is generally solved by equipment adjustment or process improvement. The third case provides an example with revising the substrate design to improve the BGA manufacturability. The simulation results and the assembly process with the new substrate design confirm that the redesign idea is available and successful.
  • Keywords
    ball grid arrays; delamination; failure analysis; finite element analysis; integrated circuit packaging; integrated circuit reliability; mass production; thermal stress cracking; BGA manufacturability; CTE mismatch; ball grid arrays; delamination; die crack; die top edge; epoxy fillets; finite element simulation; integrated circuit packaging; mass production; package development; package failure analysis; plastic deformation; problem solving; production line; stitch bond; substrate design; temperature -65 degC; temperature cycle tests; thermal stress; warpage induced process; wire heel crack; Abstracts; Delamination; Electronics packaging; Lead; Periodic structures; Plastics; Strips;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4673-1682-8
  • Electronic_ISBN
    978-1-4673-1680-4
  • Type

    conf

  • DOI
    10.1109/ICEPT-HDP.2012.6474732
  • Filename
    6474732