Robust positive-sequence detector algorithm

This paper discusses a new PLL (Phase-Locked-Loop) approach for detection of the fundamental positive-sequence component of three-phase systems. Details about this three-phase PLL structure are provided. The positive sequence detector presented computes inner-products between the input and a locally generated version of the fundamental frequency. The inner-products are used to estimate the phase-angle, frequency and amplitude of the fundamental component. In order to validate the effectiveness of the detection algorithm here discussed, simulations using PSCAD/EMTDC under conditions that are similar to the ones encountered in practical digital implementations are presented, for disturbances and unbalance. The digital implementation of this positive-sequence detector has a fast dynamic response and robust performance under distortion and/or faulty conditions when implemented using a high sampling rate and floating-point precision. For embedding such an algorithm (for example in a DSP) reducing its computational complexity is welcomed. This reduction can be approached in several ways: using fixed-point arithmetic, reducing the sampling rate or avoiding some computations. The impact of down-sampling in the inner products carried out by the algorithm (what reduces the overall computational complexity) in the performance of the algorithm is analyzed. Experimental results using a fixed-point DSP are presented as well.