DocumentCode
3505711
Title
Selective harmonic mitigation technique for multilevel cascaded H-bridge converters
Author
Napoles, Javier ; Leon, Jose I. ; Franquelo, Leopoldo G. ; Portillo, Ramon ; Aguirre, Miguel A.
Author_Institution
Electron. Eng. Dept., Univ. of Seville, Seville, Spain
fYear
2009
fDate
3-5 Nov. 2009
Firstpage
806
Lastpage
811
Abstract
The increasing demand of energy and proliferation of non-linear loads have leaded to the appearance of new grid codes which limit the maximum acceptable harmonic levels. In this context, multilevel topologies are very attractive because can generate output waveforms with a low harmonic content using a low switching frequency. In this paper, the recently presented selective harmonic mitigation technique (SHMPWM) is adapted to a nine-level converter. Its flexibility is exploited to meet the EN 50160 and CIGRE WG 36-05 grid codes without any additional filtering system using 10 switching angles per quarter of period in a wide range of amplitudes of the fundamental harmonic from 0.70 to 1.22. Some results validating this technique applied to this topology are presented. A comparison with the well known selective harmonic elimination method is included showing the advantages of the SHMPWM technique.
Keywords
bridge circuits; power convertors; power grids; power supply quality; power system harmonics; standards; CIGRE WG 36-05 grid codes; EN 50160; multilevel cascaded H-bridge converters; selective harmonic mitigation technique; Circuit topology; Filtering; Joining processes; Power engineering and energy; Power harmonic filters; Pulse width modulation; Solid state circuits; Switching converters; Switching frequency; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics, 2009. IECON '09. 35th Annual Conference of IEEE
Conference_Location
Porto
ISSN
1553-572X
Print_ISBN
978-1-4244-4648-3
Electronic_ISBN
1553-572X
Type
conf
DOI
10.1109/IECON.2009.5415023
Filename
5415023
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