A study on the highly parallel multiple-valued logic circuit design method based on the DTG

This paper proposes algorithms that design the highly parallel multiple-valued logic circuit of DTG (directed tree graph) to be represented by a tree structure relationship between the input and output of the nodes. The conventional Nakajima´s algorithms have some problems so that this paper introduces the concept of mathematical analysis based on tree structure to design an optimized locally computable circuit. Using the proposed circuit design algorithms in this paper, it is possible to design a circuit in that the DTG has any node number-not able to be designed by Nakajima´s algorithms. Also, making a comparison between the circuit design using Nakajima´s algorithms and this paper´s, we testify that the proposed algorithms in this paper optimize the circuit design all cases of DTG. Some examples are shown to demonstrate the usefulness of the circuit design algorithm