FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor

This paper shows two different FPGA implementations of a ridge extraction fingerprint algorithm. The first one is implemented by software running over a microblaze soft-processor, and the second one is based on a hardware coprocessor specifically designed to be included in an embedded authentication system. The paper compares both approaches in terms of area and speed, showing the higher performances offered by the coprocessor. Its architecture avoids the use of floating-point computations and it was segmented in several stages in order to reduce the critical path-delay. Likewise, intermediate operations are resolved in parallel leading to an increasing of the maximum clock frequency and throughput.