DocumentCode
3507013
Title
A 10 bit, 2Ms/s, 15 mW BiCMOS cyclic RSD A/D converter
Author
Garrity, Doug ; Rakers, Pat
Author_Institution
Dept. of Strategic Syst. Technol., Motorola Semicond. Products Sector, Tempe, AZ, USA
fYear
1996
fDate
29 Sep-1 Oct 1996
Firstpage
192
Lastpage
195
Abstract
A 10 bit, 2 megasamples per second (Ms/s) BiCMOS cyclic analog to digital converter (ADC) is presented. The ADC is optimized for low power operation and employs digital error correction based on the redundant signed digit (RSD) principle to correct for gain and offset errors
Keywords
BiCMOS integrated circuits; analogue-digital conversion; error correction; errors; 0.8 micron; 10 bit; 15 mW; A/D converter; BiCMOS cyclic RSD ADC; analog to digital converter; digital error correction; gain errors; low power operation; offset errors; redundant signed digit principle; BiCMOS integrated circuits; Clocks; Code standards; Digital control; Linearity; Logic circuits; Operational amplifiers; Region 1; Synchronization; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 1996., Proceedings of the 1996
Conference_Location
Minneapolis, MN
ISSN
1088-9299
Print_ISBN
0-7803-3516-3
Type
conf
DOI
10.1109/BIPOL.1996.554645
Filename
554645
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