Title :
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation
Author :
Biederman, William ; Yeager, Daniel J. ; Narevsky, Nathan ; Leverett, Jaclyn ; Neely, Ryan ; Carmena, Jose M. ; Alon, Elad ; Rabaey, Jan M.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 μA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 μs/phase, differential current of 150 μA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.
Keywords :
CMOS integrated circuits; biomedical electronics; data acquisition; neurophysiology; system-on-chip; CMOS fully-integrated neuromodulation SoC; acquisition channel; current 150 muA; current 348 muA; digital compression; frequency 100 Hz; frequency 50 Hz; simultaneous dual stimulation; voltage 1.2 V to 1.8 V; Capacitance; Capacitors; Electrodes; Gain; Noise; Power demand; System-on-chip; Adiabatic; analog; biomedical; brain-machine interface; compression; implantable electronics; low power; stimulation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2014.2384736
