Design of an optimized SRM control architecture based on a hardware/software partitioning

Author

Hilairet, Mickaël ; Hannoun, Hala ; Marchand, Claude

Author_Institution

Lab. de Genie Electr. de Paris (LGEP), Univ. Pierre et Marie Curie P6, Gif-sur-Yvette, France

fYear

2009

fDate

3-5 Nov. 2009

Firstpage

4053

Lastpage

4057

Abstract

This paper presents an effective digital speed control implementation for a switched reluctance machine. An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solution without over pending for performance or sacrificing features. Finally, the proposed strategy achieves lower current and torque ripples in a large speed range compared to a software implementation.

Keywords

control system synthesis; machine control; reluctance machines; SRM control; digital speed control; hardware/software partitioning; switched reluctance machine; system on programmable chip; Application software; Computer architecture; Costs; Design optimization; Field programmable gate arrays; Hardware; Reluctance machines; Reluctance motors; Torque control; Velocity control; FPGA; Switched reluctance machine; System on Programmable Chip; continuous and discontinuous conduction mode; hardware/software partitioning; speed control;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics, 2009. IECON '09. 35th Annual Conference of IEEE

Conference_Location

Porto

ISSN

1553-572X

Print_ISBN

978-1-4244-4648-3

Electronic_ISBN

1553-572X

Type

conf

DOI

10.1109/IECON.2009.5415107

Filename

5415107