Title :
Error suppressing encode logic of FCDL in 6-bit flash A/D converter
Author :
Ono, Koichi ; Matsuura, Tatsuji ; Imaizumi, Eiki ; Okazawa, Hisashi ; Shimokawa, Ryuushi
Author_Institution :
Semicond. & Integrated Circuit Div., Hitachi Ltd., Tokyo, Japan
fDate :
29 Sep-1 Oct 1996
Abstract :
A 6 bit, 320 Ms/s BiCMOS flash A/D converter was fabricated using a new Folded Cascoded Differential Logic (FCDL). This FCDL reduces sparkle code errors caused by comparator metastability, and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7 μm BiCMOS was less than 10-10 times/sample and the chip consumes only 505 mW
Keywords :
BiCMOS integrated circuits; analogue-digital conversion; circuit stability; coding errors; errors; logic; 0.7 micron; 505 mW; 6 bit; BiCMOS flash ADC; FCDL; comparator metastability; encoder operation speed improvement; error rates; error suppressing encode logic; flash A/D converter; folded cascoded differential logic; sparkle code errors; Bit error rate; Impedance; Latches; Logic circuits; Master-slave; Metastasis; Parasitic capacitance; Reflective binary codes; Resistors; Voltage;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1996., Proceedings of the 1996
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-3516-3
DOI :
10.1109/BIPOL.1996.554647
