A Reconfigurable Viterbi Decoder for a Communication Platform

Author

Ahmed, Imran ; Arslan, Tughrul

Author_Institution

Sch. of Electron. & Eng., Edinburgh Univ.

fYear

2006

fDate

28-30 Aug. 2006

Firstpage

1

Lastpage

6

Abstract

A new large constraint length, soft decision Viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11, and GSM. Maximum resource allocation and performance is achieved by reusing components within turbo decoder base array. This cross platform Viterbi decoder is reconfigurable between different trellis types, constraint lengths and rates making it ideal for a unified multi-standard telecommunication platform. In addition, the authors also propose a novel technique for dynamic reconfiguration in order to achieve faster context switching between different mappings. The reconfigurable fabric is implemented as a subset of turbo decoder array on a 180 nm UMC process technology

Keywords

VLSI; Viterbi decoding; system-on-chip; turbo codes; 180 nm; ADSL; CDMA2000; GSM; IEEE 802.11; UMC process technology; UMTS; WCDMA; maximum resource allocation; multi-standard telecommunication platform; reconfigurable Viterbi decoder; system on chip methodologies; turbo decoder array; Counting circuits; Decoding; Fabrics; History; Multiaccess communication; Optical wavelength conversion; Read-write memory; System-on-a-chip; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0312-X

Type

conf

DOI

10.1109/FPL.2006.311248

Filename

4101010