The Design of a 16-Channel 15 ps TDC Implemented in a 65 nm FPGA

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.