• DocumentCode
    3507977
  • Title

    Automation of IP Core Interface Generation for Reconfigurable Computing

  • Author

    Guo, Zhi ; Mitra, Abhishek ; Najjar, Walid

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Riverside, CA
  • fYear
    2006
  • fDate
    28-30 Aug. 2006
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates the generation of IP core interfaces allowing these to be used as C functions transparently from within C source codes using a reconfigurable computing compiler. We also show how this same tool can be used to support run-time reconfiguration on FPGAs by generating a common wrapper that interfaces to multiple cores
  • Keywords
    C language; field programmable gate arrays; industrial property; program compilers; reconfigurable architectures; C source codes; IP core interface generation; field programmable gate arrays; reconfigurable computing compiler; Automation; Computer interfaces; Computer science; Field programmable gate arrays; Hardware; Optimizing compilers; Productivity; Runtime; Timing; Wrapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
  • Conference_Location
    Madrid
  • Print_ISBN
    1-4244-0312-X
  • Type

    conf

  • DOI
    10.1109/FPL.2006.311254
  • Filename
    4101016