Title :
An FPGA implementation of LDPC simulation platform
Author :
Sha, Jin ; Zhang, Chuan ; Li, Li ; Minglun, Gao
Author_Institution :
Inst. of VLSI Design, Nanjing Univ. Nanjing, Nanjing, China
Abstract :
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented. As the result, a throughput of 120 Mbps is achieved and the BER curve can reach beyond 10-11 within 10 hours.
Keywords :
AWGN; block codes; decoding; error correction codes; error statistics; field programmable gate arrays; linear codes; parity check codes; AWGN noise generator; BER curve; FPGA implementation; LDPC codes performance simulation; LDPC decoder; LDPC encoder; LDPC simulation platform; bit error rate; bit rate 120 Mbit/s; error correcting performance; hardware evaluation platform; linear block codes; low-density parity-check codes; Bit error rate; Digital video broadcasting; Field programmable gate arrays; Hardware; Iterative algorithms; Iterative decoding; Multimedia communication; Parity check codes; TV broadcasting; Wireless LAN; Decoder; Error control coding; FPGA; LDPC;
Conference_Titel :
Computing, Communication, Control, and Management, 2009. CCCM 2009. ISECS International Colloquium on
Conference_Location :
Sanya
Print_ISBN :
978-1-4244-4247-8
DOI :
10.1109/CCCM.2009.5268152
