FPGA Design of A H.264/AVC Main Profile Decoder for HDTV

This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all folly H.264/AVC compliant, were completely described in VHDL and forther validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications