Title :
Interrupt management in protected mode operation of Intel 80286 high performance architecture
Author_Institution :
Dept. of Electr. & Electron. Eng., Ahsanullah Univ. of Sci. & Technol. (AUST), Dhaka, Bangladesh
Abstract :
80286 microprocessors are widely used in their protected modes in the industries for building control circuits. Implementation of the interrupt structure in protected mode is quite different from that of the real mode. The control circuit designers and the academicians prefer to use low-level assembly language programming for the understanding of the interrupt structure and other functional features of the protected mode 80286. Current literatures, textbooks and manuals have not covered much useful information in this regard. This paper accounts background studies and experimentally verified steps for the implementation of the NMI (nonmasksable) interrupt in protected mode. An interested reader could easily apply the methodology of this paper for the implementation of other interrupts.
Keywords :
assembly language; interrupts; microprocessor chips; parallel architectures; 80286 microprocessors; Intel 80286 high performance architecture; NMI interrupt; academicians; building control circuits; control circuit designers; interrupt management; interrupt structure; low-level assembly language programming; protected mode operation; IP networks; Iron; Irrigation; Logic gates; Passive optical networks; Random access memory; Descriptor; GDT Table; Interrupt Vector Table; NMI interrupt; PVAM Mode Operation; Real Mode Operation;
Conference_Titel :
Informatics, Electronics & Vision (ICIEV), 2012 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4673-1153-3
DOI :
10.1109/ICIEV.2012.6317362