A Layer Model for Systematically Designing Dynamically Reconfigurable Systems

Partial and dynamic reconfiguration significantly enhances the potential of FPGAs, which has been shown in various prototypic implementations in the past. In this paper the authors introduce a new methodology that eases the design of dynamically reconfigurable systems. It is based on a layer model that systematically abstracts from the underlying reconfigurable hardware to the application that wants to use a dynamically loaded hardware module. With six specified layers and well defined interfaces between these layers we reduce the error-proneness of the system design while increasing the reusability of existing system components. The authors demonstrate the benefits of this design methodology with two example designs: a system-on-chip implementation and a multi-FPGA approach.