Title :
The RR/RR CICQ switch: hardware design for 10-Gbps link speed
Author :
Yoshigoe, Kenji ; Christensen, Ken ; Jacob, Aju
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
The combined input and crossbar queued (CICQ) switch is an input buffered switch suitable for very high-speed networks. The implementation feasibility of the CICQ switch architecture for 24 ports and 10-Gbps link speed is shown in this paper with an FPGA-based design (estimated cost of $30,000 in mid-2002). The bottleneck of a CICQ switch with RR scheduling is the RR poller. We develop a priority encoder based RR poller that uses feedback masking. This design has lower delay than any known design for an FPGA implementation.
Keywords :
buffer storage; electronic switching systems; field programmable gate arrays; queueing theory; 10 Gbit/s; CICQ switch architecture; FPGA-based design; RR scheduling; RR/RR CICQ switch; buffered crossbar design; chassis-level design; combined input and crossbar queued switch; delay; encoder based RR poller; feedback masking; hardware design; input buffered switch; line card design; masked priority encoder; very high-speed networks; Computer architecture; Computer science; Costs; Delay; Feedback; Field programmable gate arrays; Hardware; High-speed networks; Scheduling algorithm; Switches;
Conference_Titel :
Performance, Computing, and Communications Conference, 2003. Conference Proceedings of the 2003 IEEE International
Print_ISBN :
0-7803-7893-8
DOI :
10.1109/PCCC.2003.1203733
