Design of a 3rd order CMOS sigma-delta modulator with the faster conversion rates using zero-pole canceling technique

Author

Park, Jun Han ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

Volume

1

fYear

1999

fDate

1999

Firstpage

282

Abstract

This paper proposes a new SDM (Sigma delta modulator) architecture to improve conversion rates and SNR (Signal-to noise ratio). The characteristic of the proposed SDM employs an adaptive clocking architecture which includes the first integrator with a 1 MHz clock and the second/third integrator with a 4 MHz clock. The SDM circuit with a 0.65 um CMOS process is simulated by both MATLAB and HSPICE. The simulation results illustrate that SNRs of the proposed SDM are increased by 2 dB@internal 1 bit ADC/DAC and 7 dB@3 bit and 5 bit, compared with the conventional SDM

Keywords

CMOS integrated circuits; SPICE; integrated circuit noise; poles and zeros; sigma-delta modulation; 0.65 micron; 1 MHz; 4 MHz; CMOS sigma-delta modulator; HSPICE; MATLAB; adaptive clocking architecture; circuit simulation; conversion rate; integrator; pole-zero cancellation; signal-to-noise ratio; Capacitors; Circuit noise; Circuit simulation; Clocks; Delta-sigma modulation; MATLAB; Noise cancellation; Poles and zeros; Power dissipation; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 99. Proceedings of the IEEE Region 10 Conference

Conference_Location

Cheju Island

Print_ISBN

0-7803-5739-6

Type

conf

DOI

10.1109/TENCON.1999.818405

Filename

818405