DocumentCode
350833
Title
Systolic array based on fast modular multiplication algorithm for RSA cryptosystem
Author
Kang, Min-Sup ; Kim, Dong-Wook
Author_Institution
Div. of Comput. & Electron. Eng., Anyang Univ., South Korea
Volume
1
fYear
1999
fDate
1999
Firstpage
305
Abstract
A new modular multiplication algorithm is first proposed for increasing the computation speed of addition operations and then a bit-level systolic array architecture is designed for the RSA public key cryptosystem on the basis of the algorithm. The proposed systolic array architecture has distinctive features that not only computation speed is significantly fast but also hardware overhead is drastically decreased
Keywords
digital arithmetic; parallel algorithms; public key cryptography; systolic arrays; RSA cryptosystem; addition operation; bit-level systolic array architecture; computation speed; fast modular multiplication algorithm; hardware overhead; public key cryptosystem; Algorithm design and analysis; Clocks; Computer architecture; Delay; Design engineering; Electronic mail; Hardware; Pipelines; Public key cryptography; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location
Cheju Island
Print_ISBN
0-7803-5739-6
Type
conf
DOI
10.1109/TENCON.1999.818411
Filename
818411
Link To Document