A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime

Author

Kobayashi, K. ; Kotani, M. ; Katsuki, K. ; Takatsukasa, Y. ; Ogata, K. ; Sugihara, Y. ; Onodera, H.

Author_Institution

Dept. of Commun. & Comput. Eng., Kyoto Univ.

fYear

2006

fDate

28-30 Aug. 2006

Firstpage

1

Lastpage

4

Abstract

A reconfigurable device can be utilized to enhance speed and yield on the sub-100nm device technologies, in which large within-die (WID) variations will degrade speed and cause huge yield loss in conventional fixed-structured ASICs. In the proposed scheme, configurations of all fabricated chips are optimized according to measured intra variations of LUTs and switch matrixes. Two LSIs are fabricated in a 90nm CMOS process. We successfully measured WID variations on the first LUT array LSI. The speed is enhanced by 4.1% in average on the second variation-aware FPGA LSIs to optimize configurations by the measured WID variations

Keywords

CMOS integrated circuits; application specific integrated circuits; field programmable gate arrays; reconfigurable architectures; 90 nm; ASIC; CMOS process; LUT; nanometer regime; reconfigurable devices; speed enhancement; switch matrixes; variation aware FPGA; within die variations; yield enhancement; CMOS process; CMOS technology; Degradation; Field programmable gate arrays; Large scale integration; Nanoscale devices; Semiconductor device measurement; Switches; Table lookup; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0312-X

Type

conf

DOI

10.1109/FPL.2006.311276

Filename

4101038