FPGA-Based Boundary-Scan Bist

In this paper we show how a printed circuit board (PCB) that includes a reconfigurable Field-Programmable Gate Array (FPGA) can be adapted to incorporate the capability of performing a Boundary-Scan (BS) infrastructure and interconnect self-test. The process is based on the reconfiguration of the FPGA: during the self-test procedure the FPGA is configured as a BS tester; when the test ends the FPGA is reconfigured with its functional configuration. The configuration data to perform the BS self-test is obtained from an adaptable and synthesizable VHDL model. No additional component is needed, and the hardware overhead is low: depending on the type of FPGA and the diagnostic capabilities included, between four and fourteen pins of the FPGA must keep reserved for the tester function and can not be used in the functional configuration.