Title :
Efficient multiplier architecture using optimized irreducible polynomial over GF((3n)3)
Author :
Young, Jin ; Kim, Young-Gem ; Park, Dong-Young ; Kim, Heung-Su
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
Abstract :
In this paper a multiplication algorithm over GF((3n) 3) is presented and a method of constructing a multiplier is described. The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA) and can be applied to the multiplication of polynomials over ((3n)3). By determining optimized field polynomials of degree three, the last stage of the KOA and the module reduction can be combined. Finite fields are referred to as composite fields. This is a parallel canonical basis multiplier with low gate counts and low delay. The architectures are highly modular and well suited for VLSI implementation
Keywords :
Galois fields; digital arithmetic; multiplying circuits; multivalued logic; polynomials; ternary logic; GF((3n)3); Karatsuba-Ofman algorithm; VLSI implementation; composite fields; efficient multiplier architecture; finite fields; modular architecture; multi-valued logic; multiplication algorithm; optimized irreducible polynomial; Application software; Codes; Computer architecture; Digital arithmetic; Educational institutions; Galois fields; Integrated circuit interconnections; Multivalued logic; Polynomials; Very large scale integration;
Conference_Titel :
TENCON 99. Proceedings of the IEEE Region 10 Conference
Conference_Location :
Cheju Island
Print_ISBN :
0-7803-5739-6
DOI :
10.1109/TENCON.1999.818431
