Title :
A Congestion Driven Placement Algorithm for FPGA Synthesis
Author :
Zhuo, Yue ; Li, Hao ; Mohanty, Saraju P.
Author_Institution :
Dept. of Comput. Sci. & Eng., North Texas Univ., Denton, TX
Abstract :
We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared with the linear congestion method (Betz et al., 1999) used in the state-of-the-art FPGA place and route package VPR (Betz and Rose, 1997), our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced
Keywords :
field programmable gate arrays; logic design; network synthesis; FPGA place and route package; FPGA synthesis; bounding boxes; congestion driven placement algorithm; critical path delay; linear congestion method; overlapping effect; Application specific integrated circuits; Clustering algorithms; Computer science; Delay; Field programmable gate arrays; Packaging; Programmable logic arrays; Routing; Simulated annealing; Wires;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311290
