Title :
A new auto-lock circuit concept guaranteeing low jitter in PLL frequency synthesizers irrespective of process variations
Author :
O´Sullivan, Eugene ; Kawaguchi, Manabu ; Shimoda, Akihito
Author_Institution :
Bipolar Circuit Dev. Lab., NEC Corp, Kanagawa, Japan
fDate :
29 Sep-1 Oct 1996
Abstract :
A new auto-lock circuit concept is presented for PLL synthesizers. This concept was applied to a 622 MHz embedded BiCMOS PLL. It guarantees that the PLL automatically locks at (622 MHz±10%) with less than 40 ps intrinsic peak-to-peak jitter irrespective of process variations and maintains this lockover 0°C to 125°C operating temperature range. This auto-lock circuit requires no external pins or expensive trimming process
Keywords :
BiCMOS integrated circuits; frequency synthesizers; jitter; phase locked loops; 0 to 125 C; 622 MHz; PLL frequency synthesizers; auto-lock circuit; embedded BiCMOS PLL; low jitter; Binary search trees; Clocks; Fluctuations; Frequency synthesizers; Jitter; Laboratories; Oscillators; Phase locked loops; Pins; Switching circuits;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1996., Proceedings of the 1996
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-3516-3
DOI :
10.1109/BIPOL.1996.554653
