Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Author

Krasteva, Y.E. ; de la Torre, E. ; Riesgo, T. ; Joly, Didier

Author_Institution

Univ. Politecnica de Madrid, Madrid

fYear

2006

fDate

28-30 Aug. 2006

Firstpage

1

Lastpage

4

Abstract

This paper presents a tool for Virtex II (Pro) FPGA partial bitstream manipulation suited for reconfigurable control systems with limited computing resources. The basics for partial bitstream manipulation in Virtex II (Pro) FPGAs are shown, including bit allocation equations that could be used to create such tools. After that, a tool for partial bitstream manipulation, called pBITPOS, and a use case in a reconfigurable control system are described. Differently from other non Virtex II (Pro) solutions, this tool can be integrated in a reconfiguration control system, running on an embedded device, and it can handle BRAM/MULs related data.

Keywords

embedded systems; field programmable gate arrays; reconfigurable architectures; Virtex II FPGA partial bitstream manipulation; bit allocation equation; embedded device; field programmable gate arrays; limited computing resource; reconfiguration control system; Bit rate; Clocks; Control systems; Electrical equipment industry; Equations; Field programmable gate arrays; Industrial control; Java; Logic; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0312-X

Type

conf

DOI

10.1109/FPL.2006.311298

Filename

4101060