Title :
A Segmentation Model for Partial Run-Time Reconfiguration
Author :
Taher, Mohamed ; El-Ghazawi, Tarek
Author_Institution :
George Washington Univ., Washington, DC
Abstract :
Reconfigurable computing systems have been gaining rising attention. Such systems adapt the overall system to the underlying applications at run-time. However, due to the limited reconfigurable resources, not all needed functionalities can be implemented in the same time. Previous work has considered swapping hardware functions on either a function-by-function basis or by reconfiguring the whole chip. In our previous work we have proposed a configuration management technique based on grouping related functions into fixed size blocks (pages). Pages are swapped in and out as necessary during application execution. However, paging can introduce physical artificial constraints on the grouping decision. In this work, we propose a more general virtual-memory-like technique. This technique discovers related functions and groups them into variable size blocks (segments). This, in addition to block replacement strategies can exploit both spatial and temporal processing locality simultaneously. Simulations, as well as emulation have been performed using the Cray XD1 reconfigurable computer. Results have shown that the proposed model can provide several folds of speed-up over previous techniques
Keywords :
reconfigurable architectures; Cray XD1 reconfigurable computer; artificial constraints; block replacement; configuration management; function-by-function basis; hardware functions; reconfigurable computing systems; run-time reconfiguration; virtual-memory; Bandwidth; Circuits; Computational modeling; Computer simulation; Concurrent computing; Emulation; Field programmable gate arrays; Hardware; Runtime; Supercomputers;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311305