Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions

Author

Mergens, Markus ; Wilkening, Wolfgang ; Mettler, Stephan ; Wolf, Heinrich ; Stricker, Andreas ; Fichtner, Wolfgang

Author_Institution

Robert Bosch GmbH, Reutlingen, Germany

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

1

Lastpage

10

Abstract

The detailed physical mechanisms specific to 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements/HBM testing, electron emission microscopy (EMMI) measurements, and 2D device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogenous current flow due to the unusual electrical behaviour are analyzed in single- and multifinger devices. An existing ESD-MOS compact model is extended according to the investigated phenomena. It successfully describes LDMOS high current behaviour.

Keywords

electric current; electron microscopy; electrostatic discharge; power MOSFET; semiconductor device models; semiconductor device testing; 2D device simulations; 40 V; EMMI measurements; ESD stress conditions; ESD-MOS compact model; HBM testing; LDMOS high current behaviour; LDMOS power transistors; TLP measurements; compact modeling; device topology; electrical behaviour; electron emission microscopy; gate grounded/coupled ESD stress; inhomogeneous triggering; lateral DMOS power devices; multifinger devices; single-finger devices; sustained nonhomogenous current flow; Breakdown voltage; Contact resistance; Electrical resistance measurement; Electrostatic discharge; Low voltage; Power measurement; Power transistors; Protection; Stress measurement; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.818983

Filename

818983