FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Author

Standaert, F.-X. ; Rouvroy, G. ; Quisquater, J.-J.

Author_Institution

UCL Crypto Group, Louvain-la-Neuve

fYear

2006

fDate

28-30 Aug. 2006

Firstpage

1

Lastpage

4

Abstract

This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II proreg FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec

Keywords

Boolean functions; cryptography; embedded systems; field programmable gate arrays; logic design; 128 kbit; Boolean masking; DES; FPGA implementations; Triple-DES; Xilinx Virtex-II FPGA; embedded memories; field programmable gate arrays; power analysis attacks; reconfigurable devices; substitution tables; Communication standards; Costs; Cryptography; Data security; Field programmable gate arrays; Hardware; Information security; Proposals; Protection; Smart cards;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0312-X

Type

conf

DOI

10.1109/FPL.2006.311315

Filename

4101077