Area-Efficient Implementation of a Pulse-Mode Neuron Model

In this paper the digital implementation of a pulse-mode neuron based on the voting circuit is presented. As a result of the revision and analysis on the literature, an enhanced area-saving silicon implementation of the voting circuit is presented. The optimized neuron model is hardware efficient when mapped to field programmable gate array (FPGA) technology without compromising the desirable characteristics of a sigmoid-like activation function. The FPGA implementation of the neuron model shows that the hardware utilization is lower than previous implementations especially for wide neuron receptive fields in large neural networks favoring embeddable neural processing.