An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms

This paper describes an architecture dedicated to the realtime processing of census correlation in the context of the realization of passive stereovision sensors. Although DSP circuits have dramatically increased their performances in terms of frequency (about 600 MHz today), DSP cores (several Multipliers Accumulators) and pipelines (Super Harvard Architectures for example), FPGA circuits remain the best way to design massive parallel architectures when ultra fast algorithms computation are needed like it is the case in real time vision systems for collision avoidance.