Analysis of oversampling effects on digitally controlled power supply performances

A digitally controlled power supply senses its output voltage through an error A/D converter (EADC) or an A/D converter (ADC). A voltage error signal is generated by subtracting the feedback signal from a voltage reference at a frond end amplifier. The error signal is sampled and digitized and then fed to a digital compensator. The digital compensator output is a duty cycle value, which is then loaded to a following DPWM module to generate a desired PWM signal. The EADC´s sampling position and sampling rate, digital filter´s computing speed and DPWM´s updating timing all directly affect the control loop´s performance. Among these, oversampling (multiple samplings over one switching period) is one of the most effective methods to reject noise and to improve signal measurement accuracy and control loop performance. Effects of oversampling are analyzed. Detailed simulated data and test data on a PFC converter and a DC/DC converter are also provided.