FPGA Implementation of High-Performance PHM / DPHM Schedulers

Author

Soto, Enrique ; Lago, Elena ; Rodríguez-Andina, Juan J.

Author_Institution

Dept. of Electron. Technol., Vigo Univ.

fYear

2006

fDate

28-30 Aug. 2006

Firstpage

1

Lastpage

4

Abstract

One of the most important issues in current high-performance packet switches is the availability of efficient algorithms to maximize instantaneous throughput. The PHM (parallel hierarchical matching) algorithm and its decoupled version, DPHM, are recently proposed distributed maximal size matching scheduling algorithms for virtual output-queued switches. In this paper, the design and evaluation of PHM/DPHM schedulers implemented in FPGAs is presented and discussed. Experimental results show that, in addition to the well-known advantages of using field-programmable logic, the proposed implementations provide a performance level which makes them a suitable alternative to ASICs for high-performance scheduling tasks

Keywords

field programmable gate arrays; packet switching; scheduling; FPGA; decoupled parallel hierarchical matching; distributed maximal size matching scheduling; field-programmable logic; packet switches; virtual output-queued switches; Application specific integrated circuits; Field programmable gate arrays; Hardware; Iterative algorithms; Packet switching; Prognostics and health management; Scheduling algorithm; Software algorithms; Switches; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2006. FPL '06. International Conference on

Conference_Location

Madrid

Print_ISBN

1-4244-0312-X

Type

conf

DOI

10.1109/FPL.2006.311326

Filename

4101088