FPGA Implementation of High-Performance PHM / DPHM Schedulers

One of the most important issues in current high-performance packet switches is the availability of efficient algorithms to maximize instantaneous throughput. The PHM (parallel hierarchical matching) algorithm and its decoupled version, DPHM, are recently proposed distributed maximal size matching scheduling algorithms for virtual output-queued switches. In this paper, the design and evaluation of PHM/DPHM schedulers implemented in FPGAs is presented and discussed. Experimental results show that, in addition to the well-known advantages of using field-programmable logic, the proposed implementations provide a performance level which makes them a suitable alternative to ASICs for high-performance scheduling tasks