Title :
Influence of gate length on ESD-performance for deep sub micron CMOS technology
Author :
Bock, K. ; Keppens, B. ; Heyn, V. De ; Groeseneken, G. ; Ching, L.Y. ; Naem, A.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
The ESD performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 /spl mu/m CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD thresholds, leading to an optimum performance for longer gate length devices attributed to the trade-off between power dissipation and melt volume of the parasitic bipolar device.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit testing; protection; 0.25 micron; CMOS epitaxial layer based technology; CMOS technology; ESD performance; ESD threshold; gate length; grounded-gate nMOS protection structures; melt volume; optimum performance; parasitic bipolar device; power dissipation; Bipolar transistors; Breakdown voltage; CMOS technology; Current measurement; MOS devices; Power dissipation; Pulse measurements; Silicides; Stress; System testing;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999
Conference_Location :
Orlando, FL, USA
Print_ISBN :
1-58637-007-X
DOI :
10.1109/EOSESD.1999.818995
